In electronic design and verification, raising design abstraction levels generally increases productivity by speeding up the design and verification process. Electronic design involves creation and verification of hardware. However, a design process is delayed by manually writing register transfer level (RTL) descriptions having the same functions as a high level specification model written in a high-level language such as C, C++, or SystemC®. Thus, hardware design would be improved and accelerated by automatic translating high level specification models to RTL models. One type of translator is the C-to-Silicon (CtoS) compiler. The CtoS compiler reads a high-level language description of hardware architecture and generates a Verilog RTL micro-architecture using high-level constraints unique to a target product's requirements and process library. The constraints may be modified based on visual feedback from a graphical design environment and incremental database. However, some functions related to analysis of CtoS-generated RTL models require analysis of the high-level language source code, which may be challenging or tedious for a user. Thus, there exists a need in the art to make features of a CtoS compiler more user-friendly.